1. Field of the Invention
The present invention relates to the field of electrical interconnection technologies for microelectronics system elements. In particular, the present invention relates to methods for producing electrical through hole interconnects.
2. Description of the Related Technology
The evolution of VLSI technology calls for an increasing bandwidth of interconnects between IC's and/or other system elements. For short interconnects, electrical signal lines maintain the highest capacity and speed. In order to keep up with the increasing speed and density requirements, system in a package (SIP) technology is increasingly used. This creates the need for 3-dimensional interconnects.
An example of the fabrication of such interconnects can be found in U.S. Pat. No. 6,184,060. Vias or through holes are made in the front side of the wafer, and dielectric and contact pad metal are deposited into the vias. Then the wafer back side is etched until the back metal is exposed. This method requires the back side to be etched up to the contact pad, including etching the dielectric deposited on the bottom of the vias. The patent indicates silicon oxide or BPSG as material for the dielectric, deposited by CVD (Chemical Vapor Deposition). Also thermal oxidation is mentioned. Etching silicon oxide with respect to silicon is not trivial and cannot be done anistropically. Silicon oxide deposition produces layers with essentially uniform thickness, which limits design freedom.